|
June 27,
2007
Microsoft Windows* 2000
Microsoft
Windows* XP
INTEL CONFIDENTIAL
DISCLAIMER: Information in this document is
provided in connection with Intel products. No license, express or implied,
by estoppel or otherwise, to any intellectual property rights is granted
by this document. Except as provided in Intel’s Terms and Conditions of Sale
for such products, Intel assumes no liability whatsoever, and Intel disclaims
any express or implied warranty relating to sale and/or use of Intel
products, including liability or warranties relating to fitness for a
particular purpose, merchantability or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use
in medical, lifesaving, or life-sustaining applications.
Intel may make changes to specifications and product
descriptions at any time, without notice.
Contact your local Intel sales office or your distributor
to obtain the latest specifications and before placing your product order.
* Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation 2006-2007
This document contains information on products in the
design phase of development. The information herein is subject to change
without notice. Do not finalize a design with this information.
Revision History
|
Date
|
Driver Revision
|
Description
|
Build Number
|
|
June 27, 2007
|
Production Version 6.14.10.4847
|
Production Version ; Fully
validated
|
4847
|
|
June 12, 2007
|
Production Version 6.14.10.4837
|
Production Version ; Fully
validated
|
4837
|
|
May 31, 2007
|
Production Version 6.14.10.4833
|
Production Version ; Fully
validated
|
4833
|
|
May 30, 2007
|
Production Candidate 6.14.10.4833
|
Production Candidate ; Fully
validated
|
4833
|
|
April 19, 2007
|
Production Version 6.14.10.4820
|
Production Version ; Fully
validated
|
4820
|
|
April 19, 2007
|
Production Candidate 6.14.10.4820
|
Production Candidate; Fully
validated
|
4820
|
|
March 15, 2007
|
Beta 6.14.10.4793
|
Weekly engineering drop; not
fully validated
|
4793
|
|
March 2, 2007
|
Beta 6.14.10.4786
|
Weekly engineering drop; not
fully validated
|
4786
|
|
February 15, 2007
|
Beta 6.14.10.4775
|
Weekly engineering drop; not
fully validated
|
4775
|
|
February 1, 2007
|
Beta 6.14.10.4770
|
Weekly engineering drop; not
fully validated
|
4770
|
|
January 18, 2007
|
Alpha 6.14.10.4762
|
Weekly engineering drop; not
fully validated
|
4762
|
|
January 4, 2007
|
Alpha 6.14.10.4755
|
Weekly engineering drop; not
fully validated
|
4755
|
|
December 21, 2006
|
Alpha 6.14.10.4752
|
Weekly engineering drop; not
fully validated
|
4752
|
|
December 12, 2006
|
Alpha 6.14.10.4742
|
Weekly engineering drop; not
fully validated
|
4742
|
|
December 1, 2006
|
Pre-Alpha 6.14.10.4721
|
Weekly engineering drop; not
fully validated
|
4721
|
|
October 30, 2006
|
Pre-Alpha 6.14.10.4720
|
Weekly engineering drop; not
fully validated
|
4720
|
|
October 23, 2006
|
Pre-Alpha 6.14.10.4717
|
Weekly engineering drop; not
fully validated
|
4717
|
Intel®
Graphics Media Accelerator Driver
The Intel® Graphics Media
Accelerator Driver contains support for the following Intel Chipsets:
·
Intel® Q33/Q35/G33 Chipset
·
Intel® 945G Express Chipset
·
Intel® 945GZ Express Chipset
·
Intel® 946GZ Express Chipset
·
Intel® G965 Express Chipset
·
Intel® Q963 Express Chipset
·
Intel® Q965 Express Chipset
·
Mobile Intel® 940GML Express Chipset
·
Mobile Intel® 943GML Express Chipset
·
Mobile Intel® 945GM Express Chipset
·
Mobile Intel® 945GMS Express Chipset
·
Mobile Intel® GM965 Express Chipset
New
Features
|
Features
Added in Baseline
|
|
Reference
No.
|
Description
|
|
957217
|
Entry
point for MPEG2 Variable Length Decode and Inverse Discrete Cosine
Transformation
|
|
946854
|
Intel®
Smart 2D Display Technology and Intel® Rapid Memory Power Management
enable, disable API via CUI SDK
|
|
978877
|
ProcAmp
Support
|
|
979457
|
DVMT
4.0 Support
|
|
|
Programmable
SDVO Specialty Feature
|
|
981503
|
Capture EDID Raw Data in CUI
|
|
979481
|
Clear
Video Technology API and App Readable Flag
|
|
962997
|
Intel®
TV Wizard
|
|
954349
|
Small
VBIOS
|
|
995144
|
Turn
off idle second display pipe for desktop power savings
|
|
N/A
|
Virtualization
Technology for Device I/O
|
Known Issues
|
Known
Issues 14.29.3.4847
|
|
103718
|
The display mode is not switched to LFP, TV, EFP,
LFP+EFP DDC in order via pressing ACPI hotkeys with modified BIOS
|
Unknown
|
Windows* XP
|
Intel® GM965 Express Chipset
|
|
103339
|
IGT page and Device Manager page cannot refresh
automatically after unplugging the HDTV and then hot plugging the SDTV with
LFP+TV DDC mode.
|
CUI2
|
Windows* XP, Windows* XP-64
|
Intel® 945GM Express Chipset
Intel® GM965 Express Chipset
|
|
102500
|
Corruption is displayed on the Overfly application with
640x480x8bit @ 60Hz on 90 degrees after launching the THRASH_MODES
application.
|
DirectDraw*
|
Windows* XP-64
|
Intel® 945GM Express Chipset
|
|
100765
|
GLTunnel - error
message is displayed after resuming from Suspend state(S3).
|
OpenGL*
|
Windows Media Center, Windows*
XP, Windows* XP-64
|
Intel® 3 Series Chipset Family-B
Intel® G965 Express Chipset
Intel® 945GM Express Chipset
Intel® GM965 Express Chipset
|
|
99056
|
Display cannot be
rotated via Desktop Context Menu\ Graphics Options\ Rotation with DDT
display mode.
|
CUI2
|
Windows* XP, Windows* XP-64
|
Intel® 3 Series Chipset Family-B
Intel® G965 Express Chipset
Intel® 945GM Express Chipset
Intel® GM965 Express Chipset
Intel® 945G Express Chipset
|
|
99496
|
Flicker and white playback is displayed on Direct3D*_TunnelDP
application with fullscreen mode after rotating display to 180 degree.
|
Rotation
|
Windows* XP, Windows* XP-64
|
Intel® 3 Series Chipset Family-B
Intel® G965 Express Chipset
Intel® 945GM Express Chipset
Intel® GM965 Express Chipset
|
|
99121
|
Display mode change to CRT only mode after opening lid
switch from Suspend state (S3) with modified BIOS.
|
NT - miniport
|
Windows* XP
|
Intel® GM965 Express Chipset
|
Issues
Resolved
|
Issues
Resolved in Build 4847
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID: 2449575
|
XP driver fails on 945/965 GME
platform
|
CUI COM
|
Windows* 2000, Windows* XP, Windows* 20003, Windows Media
Center, Windows* XP-64, Windows*
20003-64, Windows Vista*, Windows Vista*-64
|
Intel® G965 Express Chipset
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: Device
Id's for these skus were not communicated to CUI
|
|
Issues
Resolved in Build 4837
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID: 2440145
|
Chrontel sDVO CRT is not detected
|
AIM Module
|
Windows* XP
|
Intel® 3 Series Chipset Family-B
|
|
Resolution Description:
Root Cause: Issue: SDVO VGA is not detected after unplug and plug in
clone configuration. Root cause: On Windows Vista*, the port and pipe are
turned off when CRT is not detected, at this moment the input clock is also
turned off,but SetActiveOutput() still programmed to RGB output (02H) at
previous status which forces CH7021 to use input clock as clock source to
do the connection detection. since there is no reference clock input to
CH7021 for doing the detection, CH7021 keeps trying to detect which DAC is
connected continuously and finally return “ SDVO_PENDING” status.
|
|
BugID: 2443988
|
Display connected via DVI-to-VGA cannot be enabled; DVI-D
OK
|
AIM Module
|
Windows* XP
|
Intel® 3 Series Chipset Family-B
|
|
Resolution Description:
Root Cause: Issue: No
display on DVI-I->VGA. Root cause: Input-output mapping was incorrect.
|
|
Issues
Resolved in Build 4833
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID:
N/A
|
CUI2 Localization merge to INT_14.29 branch for linguistic fixes.
|
CUI2
|
Windows* XP, Windows* XP-64
|
Intel® 3 Series Chipset Family-B
|
|
Resolution
Description:
Root Cause: Fixed drop-down list issue in the Hot Keys tab; fixed cut
text issue in Display Devices; fixed one corrupted character.
|
|
BugID:
2445585
|
HSYNC polarity for the overscan mode was not as per the
spec.
|
Soft BIOS
|
Windows* XP, Windows* XP-64, Windows Vista*, Windows Vista*-64
|
Intel® 945GM Express Chipset
|
|
Resolution
Description:
Root Cause: 1184x666 50Hz (for 720p 50Hz format) HSYNC polarity is
wrong.
|
|
BugID:
N/A
|
New Intel® 945GM Express Chipset / Intel® GM965 Express
Chipset device IDs.
|
TVout, INF File
|
Windows* 2000, Windows* XP, Windows* 20003, Windows Media
Center, Windows* XP-64, Windows*
20003-64, Windows Vista*, Windows Vista*-64
|
Intel® 915GM Express Chipset
Intel® 945G Express Chipset
Intel® G965 Express Chipset
Intel® GM965 Express Chipset
Intel® 3 Series Chipset Family
|
|
Resolution
Description:
Root Cause: New device IDs have been added for Intel® 945GM Express
Chipset and Intel® GM965 Express Chipset to support new SKUs.
|
|
BugID:
2436863
|
W - DTM
- Stretch Rect (32-bit) - Log Failure
|
D3D
|
Windows* XP, Windows* XP-64
|
Intel® GM965 Express Chipset
|
|
Root
Cause:
Fix Description: Sync flush to behave like other platforms
|
|
BugID:
2439669
|
can not
show 1440x900 resolution on PW201 Monitor
|
SoftBIOS
|
Windows* 2000, Windows* XP, Windows
Media Center,
Windows* XP-64, Windows* 20003-64, Windows Vista*, Windows Vista*-64
|
Intel® G965 Express Chipset
Intel® 3 Series Chipset Family
|
|
Root
Cause: While
parsing Standard Timing, it was wrongly compared for unused value
Fix Description:
|
|
BugID:
2441543
|
Functional
Failure/ DVD: Driver Verification (AUTO) - CUI is not installing with
Graphics driver
|
CUI2
|
Windows* XP, Windows* XP-64
|
Intel® 3 Series Chipset Family
|
|
Root
Cause: the
device id’s were missing under getgraphicsfamilyname
Fix Description:
|
|
BugID:
2439927
|
MV Copp
Violation for QueryDisplay Details
|
NT-miniport
|
Windows* 2000, Windows* XP, Windows
Media Center,
Windows* XP-64, Windows* 20003-64, Windows Vista*, Windows Vista*-64
|
Intel® 945GM Express Chipset
Intel® GM965 Express Chipset
|
|
Root
Cause:
Fix Description: This change is related to UAIM sending STATUS_SUCCESS
even after executing the Opcode for setting MV on NON MV Compatible TV
Standard
|
|
BugID:
2440145
|
Macao- Chrontel sDVO CRT is not detected
|
AIM
module
|
Windows* 2000, Windows* XP, Windows
Media Center,
Windows* XP-64, Windows* 20003-64, Windows Vista*, Windows Vista*-64
|
Intel® 945GM Express Chipset
Intel® 3 Series Chipset Family
|
|
Root
Cause: The port
and pipe are turned off when CRT is not detected, at this moment the input
clock is also turned off,but SetActiveOutput() still programmed to RGB
output (02H) at previous status which forces CH7021 to use input clock as
clock source to do the connection detection. since there is no reference
clock input to CH7021 for doing the detection, CH7021 keeps trying to
detect which DAC is connected continuously and finally return “
SDVO_PENDING” status.
Fix Description: Changed the arguement from
pAimObj->dwConnectedOutputs to pAimObj->dwOutputs while calling
EnableDisableOutputs() to turnoff display.
|
|
BugID:
2445585
|
1184x666
50Hz (for 720p 50Hz format) HSYNC polarity is wrong.
|
AIM
module
|
Windows* XP, Windows* XP-64
|
Intel® 945GM Express Chipset
|
|
Root
Cause: HSYNC
polarity for the overscan mode was not as per the spec.
Fix Description:
|
|
|
BugID:
2443549
|
ACPI
display change event doesn't work after hot plug of CRT
|
NT-miniport
|
Windows* 2000, Windows* XP, Windows Media
Center, Windows*
XP-64
|
Intel® GM965 Express Chipset
|
|
Root
Cause:
Fix Description: Driver to handle the _DGS IRP in failing scenarios so
the Miniport Driver is notified of all Hotkey Events
|
|
|
BugID:
2437960
|
A
display playing WMV9 movie collapses after "Windows Media Format
Runtime 9.5" was installed.
|
DVD
|
Windows* 2000, Windows* XP, Windows Media
Center, Windows*
XP-64
|
Intel® GM965 Express Chipset
|
|
Root
Cause: The
pass-in intensity compensation flag is wrong
Fix Description:
|
|
|
|
|
|
|
|
|
BugID:
2444396
|
White
color screen or garbage on LFP after installing driver.
|
SoftBIOS
|
Windows* 2000, Windows* XP, Windows
Media Center,
Windows* XP-64, Windows* 20003-64, Windows Vista*, Windows Vista*-64
|
Intel® GM965 Express Chipset
|
|
Root
Cause:
Fix Description: For Automatic Selection we will check the Port Register
bits to decide no. of channels the LFP has, which VBIOS updates properly
|
|
|
BugID:
2443806
|
System
hang running graphics stress apps
|
D3D, DD, DVD, GDI, GHAL3D, NT - miniport
|
Windows* 2000, Windows* XP, Windows
Media Center, Windows* XP-64, Windows* 20003-64, Windows Vista*, Windows
Vista*-64
|
Intel® 945G Express Chipset
Intel® 945GM Express Chipset
|
|
Root
Cause:
Fix Description: Disabling lazy writes resolves the GlitchII/D3D hang
caused by 3D indirect state corruption occurring during context switches
|
|
|
|
|
|
|
|
|
|
|
|
|
BugID:
2441684
|
LCD
brightness does not change from Fn+Home/End key.
|
Power
Conservation
|
Windows* XP, Windows* XP-64
|
Intel® GM965 Express Chipset
|
|
Root
Cause: LBB
interrupt was not generated
Fix Description:
|
|
|
Issues
Resolved in Build 4820
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID: 2333313,
2334906, 2436382, 2439343
|
Extended Second Display using the integrated video card
shows blank after wakeup from sleep.
|
Resource Manager
|
Windows* XP, Windows* XP-64
|
Intel® 3 Series Chipset Family-B, Intel® G965 Express
Chipset, Intel® 945GM Express Chipset, Intel® GM965 Express Chipset, Intel®
945G Express Chipset
|
|
Resolution Description:
Root
Cause: In DPDD S3/Resume, Secondary Bandwidth is getting
added up twice leading to bandwidth leakage. Bandwidth exhaust after couple
of S3/Resum calls. This is due to change in ED call sequence for Windows
Vista* in case of S3/Resum. In this case, Secondary SPSD call comes first
unlike normal sequence where Primary SPSD comes. This is leading to
overwriting GRM structures leading to wrong bandwidth calculations.
Fix Description: To avoid previous bandwidth issues also ported fix
changes done for Issue # 2292924 which was checked into main but not 15.2.
This fix removes the dependency of sequence calls. Cache the Value of
AttchedDisplayUID in DPDD primary case and use this to decide upon
bandwidth allocation for both primary and secondary. This fix takes care of
using right values for calculating bandwidth.
|
|
BugID: 2332069
|
The display blank out for DDC CRT+DFP applied through
context menu.
|
CUI2
|
Windows* XP, Windows* XP-64
|
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root
Cause: The issue was happening because with CRT+LFP, CRT
does not support 58 hz.
Fix Description: In validateConfig(), we check whether the RR is in
modelist or not. If not, we pass the defualt RR 60Hz to driver.
|
|
Issues
Resolved in Build 4793
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID: 2256822
|
Image corrupted when Present operation is performed to a
Primary in LINEAR format.
|
Miniport, SoftBIOS
|
Windows* XP, Windows* 2000 Windows* XP-64, Windows Vista*,
Windows Vista*-64
|
Intel® G965 Express Chipset, Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: There were 2
issues here with respect to handling dynamic change in surface format in
Windows Vista* without a mode change. 1) In Miniport where only the
parameter would get updated if it was Tiled. So, Linear-->Tiled was
taken care of, but Tiled-->Linear changes were missing.
Fix Description: Fix was to handle this for cases which
would result in subsequent update of the Plane registers viz. 2) In SB
where it assumed that surface format would not change without an
EnablePlane. Corrected the logic to always set the tileX bit (Bit10) in
Plane Control Register appropriately depending on Tiled or Linear format.
Miniport functions which change Plane start addr -
Topology_SetSourceAddress and Topology_SetFlip. Also fixed another issue of
updating gamma in 8bpp modes via CUI path- ComSetGamma.
|
|
BugID: 2332452
|
LFP Polarity of H-Sync and V-Sync are incorrect.
|
SoftBIOS
|
Windows* XP, Windows Vista*
|
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root
Cause: In GetLVDSTimingInfo(), we were not getting the
flags from the DTD timing and we were saving the restoring the values as
were before. Because of the above, even if we specify the Negative polarity
in the DTD timing, we were not actually populating the same in the flags.
So the register 61180 was not getting updated with proper polarity. It is
always set to default values.
Fix Description: Changes are done along with the timing. Also populate
the Flags taken from DTD timing and removed the code of save and restore.
|
|
BugID: 2077788,
2329497
|
Adding
new indirect state model for handling CURBE data and surface
states. This model changes default model from a caching model to a
streaming model, however both models still exist in the code. Tests ran on
3Dmark03, 3DMark05, 3DMark06, FEAR, Sims2, Quake3, Doom3 on XP, and
3DMark03 on Vista.
|
D3D, GHAL3D, OGL
|
Windows* XP, Windows* XP-64, Windows Vista*, Windows Vista*-64
|
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root
Cause: GHAL3D CURBE and Surface State
Streaming Optimization.
Fix Description:
|
|
Issues
Resolved in Build 4786
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID: 2329076,
2327752, 2329076
|
ACPI Hot Keys will not work after hot plug for the first
time.
|
Miniport
|
Windows* 2000, Windows* XP, Tablet Pc, Windows* 20003,
Windows* XP-64, Windows* 20003-64
|
Intel® 945GM Express Chipset, Intel® GM965 Express
Chipset
|
|
Resolution Description:
Root Cause: Event Manager Display List was not getting updated
during enumeration which is the list used while validating the
configuration to be set after hotkeys in the function EM_ValidateConfig.
Fix Description: Since this function was only being used in another
place apart from above where we do Display Switch in FSDOS, we removed the
device list connectivity check which will fix the issue. So basically we
are not updating the Event Manager Display List during enumeration as
mentioned in previous description. The reason was that to allow event
manager display list to be populated as need based on the events and flags
rather during enumeration.
|
|
BugID: 2077788,
2329497
|
GHAL3D CURBE and Surface State
Streaming Optimization.
|
Direct3D*, GHAL3D, OpenGL*
|
Windows* XP, Windows* XP-64, Windows Vista*, Windows Vista*-64
|
Intel® G965 Express Chipset
|
|
Resolution Description:
Root Cause: Adding new
indirect state model for handling CURBE data and surface states. This model changes default model from a
caching model to a streaming model, however both models still exist in the
code. Tests ran on 3Dmark03, 3DMark05, 3DMark06, FEAR, Sims2, Quake3, Doom3
on Windows* XP, and 3DMark03 on Windows Vista*.
|
|
BugID: 2326223
|
Video fades in and out when resuming from hibernation. (Porting
into PC14.27 branch)
|
SoftBIOS
|
Windows Vista*, Windows Vista*-64
|
Intel® 945GM Express Chipset, Intel® GM965 Express
Chipset
|
|
Resolution Description:
Root Cause: Optimize the
persitence code which was causing too many flickers.
|
|
BugID: 2288162
|
Fix failures in DTM StretchRect test in BW-G Windows* XP.
(TIBET
#2288162)
|
Direct3D*
|
Windows* XP
|
Intel® G965 Express Chipset, Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: The first
failing test #12316 has a resource that is a flip chain (front buffer +
back buffer). We called SurfaceBlt() with dstSubResourceIndex = 1, but did
not pass this index to D3DBltSrc(). In D3DBltSrc(), we recalculated the
index = 0. So we were copying to the dst surface with index 0 instead of
the surface with index 1. That was why the square sky image was missing. To
fix the tests, we need to pass in the dstSubResourceIndex (and
srcSubResourceIndex) to D3DBltSrc(). This re-test is only to test Windows*
XP drivers. The changes do not touch Windows Vista*. StretchRect, 3DMark05,
has been tested.
|
|
BugID: 2255316
|
Adding support for Continue and While Labels.
|
Direct3D*, GHAL3D, OpenGL*
|
Windows* XP, Windows* XP-64, Windows Vista*, Windows Vista*-64
|
Intel® G965 Express Chipset
|
|
Resolution Description:
Root Cause: Add support
for "Continue" and "While" Labels to more accurately
target jump destinations for these instructions. Also lay the groundwork
for function calls.
|
|
BugID: 2255316
|
DX10 Framework Changes.
|
Direct3D*, GHAL3D, OpenGL*
|
Windows* XP, Windows* XP-64, Windows Vista*, Windows Vista*-64
|
Intel® G965 Express Chipset, Intel® G965 Express Chipset,
Intel® 945GM Express Chipset, Intel® GM965 Express Chipset, Intel® 945G
Express Chipset
|
|
Resolution Description:
Root Cause: The DX10
framework includes the files necessary to compile the D3D10 dlls. For the
most part these changes will have a minimal impact on D3D9. There are some
changes to D3D9 and GHAL2D to support the new GHAL3D interface changes in
this drop which require the ETM. There are also some small changes to
GHAL3D internal implementation to support DX10. Inf changes were also
necessary to properly install the D3D10 dll if it was built prior to
makefile execution.
|
|
BugID: 2173326
|
Doom3 Gen3 Windows Vista*
Hang Fix.
|
OpenGL*
|
Windows* XP, Windows* XP-64, Windows Vista*, Windows Vista*-64
|
Intel® 3 Series Chipset Family-B, Intel® G965 Express
Chipset, Intel® 945GM Express Chipset, Intel® 945G Express Chipset
|
|
Resolution Description:
Root Cause: Fixes Doom3
on Windows Vista* Intel® 945G Express
Chipset, Intel® 3 Series Chipset Family, and Intel® 945GM Express Chipset.
This issue was caused by OpenGL programming GHAL3D with an improper state
setting.
|
|
Issues
Resolved in Build 4775
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID: 2077576,
2326924
|
GHAL3D VS - constant buffer optimization for indirectly
addressed constants.
|
Direct3D*, GHAL3D, OpenGL*
|
Windows* XP, Windows* XP-64, Windows Vista*, Windows Vista*-64
|
Intel® G965 Express Chipset, Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: Optimization
for HW vertex processing. This optimization gets applied for workloads
containing constants with indirect registers. This optimization will
attempt to batch up 'send' instructions to minimize the number of sends
that we make.
|
|
BugID: 2326537
|
Incorrect Adapter Chip Type String for G965.
|
Miniport
|
Windows* 2000, Windows* XP, Tablet Pc, Windows* 20003,
Windows Media* Center, Windows*
XP-64, Windows* 20003-64, Windows Vista*, Windows Vista*-64
|
Intel® G965 Express Chipset
|
|
Resolution Description:
Root Cause: To change the
Chip Type string for G965 Broadater chipset to "Intel(R) GMA
X3000" instead of "Intel(R) GMA3000".
|
|
BugID: 2325767
|
DXVA encryption memory leak.
|
DVD
|
Windows* XP, Windows Media* Center, Windows Vista*
|
Intel® 3 Series Chipset Family-B, Intel® G965 Express
Chipset, Intel® G965 Express Chipset, Intel® 945GM Express Chipset, Intel®
GM965 Express Chipset
|
|
Resolution Description:
Root Cause: An unexpected
usage model of DXVA encryption in which encryption is toggled On and Off
with the same video session caused a memory leak because the scratch memory
for encryption was reallocated over and overwithout being freed. The
solution is simply only to allocate the scratch surface once and then check
it before allocating again.
|
|
BugID: 2291781
|
When HDMI is connected devicename in SystemPage, Device
tab is not in sync.
|
CUI2
|
Windows Vista*, Windows*
XP
|
Intel® 945GM Express Chipset
|
|
Resolution Description:
Root Cause: While loading
the strings for Digital display in information page, the check for HDMI TV
was missing.
|
|
BugID: 2255351
|
Panel Fitting changes for Windows* XP and Windows Vista*.
|
Miniport, Power Conservation
|
Windows* 2000, Windows* XP, Windows* XP-64, Windows
Vista*, Windows Vista*-64
|
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: Purpose: This
changes were intended to support Panel Fitting via BIOS hotkeys. Details:
The support was required for both Windows* XP and Windows Vista*. To
Support panel fitting it required some changes in handling ASLE event.
|
|
BugID: 2255316
|
Removal of compiler and linker warnings in Direct3D*,
DIRECTDRAW*, and GHAL2D components.
|
Direct3D*, DirectDraw*, OpenGL*
|
Windows* XP, Windows* XP-64, Windows Vista*, Windows Vista*-64
|
Intel® 3 Series Chipset Family-B, Intel® G965 Express
Chipset, Intel® G965 Express Chipset, Intel® 945GM Express Chipset,
Cantiga, Intel® GM965 Express Chipset, Intel® 915G Express Chipset, Intel®
945G Express Chipset
|
|
Resolution Description:
Root Cause: This check-in
addresses the many compiler and linker warnings seen in the Direct3D*,
DIRECTDRAW*, GHAL2D, and some of the warnings in GHAL. Also the "Error
on warning flag" has been turned on for all components and
configurations except GHAL. (The GMM team has some work to do to address
the rest of the warnings in GHAL.)
|
|
BugID: 2255316
|
Fix using namespace GHAL3D in GHAL2D.
|
Direct3D*, DirectDraw*, DVD, GDI
|
Windows* XP, Windows Vista*
|
Intel® G965 Express Chipset
|
|
Resolution Description:
Root Cause: This DCN
removes the "using namespace GHAL3D" from the GHAL2D files.
Instead we will be prepending GHAL3D:: to all GHAL3D types to avoid naming
conflicts.
|
|
BugID: 2255316
|
Dynamic URB Allocation.
|
Direct3D*, GHAL3D, OpenGL*
|
Windows* XP, Windows Vista*
|
Intel® G965 Express Chipset
|
|
Resolution Description:
Root Cause: Change
allocation of URB space from a static model based on enabled fixed function
units to a dynamic model based on vertex size, per fixed function URB space
requirements, and an algorithm for optimal distribution of space.
|
|
Issues
Resolved in Build 4770
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID: 2255620,
2257115
|
Display mode cannot be switched on CRT only mode via
pressing the ACPI hot key.
|
Miniport
|
Windows* 2000,
Windows* XP,
Windows* 20003,
Windows Media*
Center,
Windows* XP-64,
Windows* 2003-64,
Tablet Pc
|
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: There are two
issues targetted with this code fix. One is 2255620 and another is 2257115.
For details on issues, please refer to the peer review document in the
attachment. These issues are resolved in the latest version of Os and we
could not reproduce them later. So, passing the EMT as passed with issues
as we have found 14 production sightings which will be attached to the DCN.
|
|
BugID: 2194906,
2221920, 2287914,
|
Fix for DCN516790's Breaking Pre-Intel® Q33/Q35/G33
Express Chipsets OpenGL*.
|
OpenGL*
|
Windows* 2000,
Windows* XP,
Windows* 2003,
Windows Media* Center,
Windows* XP-64,
Windows* 2003-64,
Tablet Pc
|
Intel® 915GM Express Chipset,
Intel® 945GM Express Chipset,
Intel® 915G Express Chipset,
Intel® 945G Express Chipset,
|
|
Resolution Description:
Root Cause: DCN516790 had
OpenGL* pass the GMM a __GMM_NO_GPU_ONLY flag to let the GMM know OpenGL*
is not interested in receiving GPU_ONLY memory. The flag passing was meant
to be atemporary fix (until OpenGL* adds GPU_ONLY support), and since the
GMM was out of usable flag bits for this purpose, the __GMM_NO_GPU_ONLY is
actually the GMM_ GPU_ONLY flag, being used for a second purpose. GMM
support was only implemented to have OpenGL* to pass this flag in on >=
Bearlake, but the OpenGL* implementation passes the flag in on all
platforms. This breaks things when the GMM gets the unexpected flag on
pre-Bearlake platforms. This fix is simply to have OpenGL* only pass-in the
__GMM_NO_GPU_ONLY flag on platforms >= Bearlake (BLB + >= Gen4).
|
|
BugID: 2194906,
2221920, 2287914
|
Adding SW-Tiling Copy Engine to support 384MB DVMT GPU
per surface tiling.
|
Direct3D*,
DirectDraw*,
DVD,
GMM,
OpenGL*
|
Windows* 2000,
Windows* XP,
Windows* 2003,
Windows Media* Center,
Windows* XP-64,
Windows* 2003-64,
Tablet Pc
|
Intel® Q33/Q35/G33 Express Chipsets,
Intel® G965 Express Chipset,
Intel® 945GM Express Chipset,
Intel® GM965 Express Chipset,
Intel® 945G Express Chipset,
|
|
Resolution Description:
Root Cause: We are
tacking-on to the DCN (post-ETM) a registry setting with which we can
control the GPU_ONLY allocation system--So tiled GPU_ONLY or all of
GPU_ONLY can be disabled if necessary.
|
|
BugID: 2102022,
2255316
|
Gen5+ GHAL3D updates and fixes.
|
Direct3D*,
GHAL3D,
OpenGL*
|
Windows* XP,
Windows Vista*
|
Intel® G965 Express Chipset
|
|
Resolution Description:
Root Cause: 1) Change
line antialias alpha value from U0.4 to U0.8 when performing line
antialiasing in the pixel shader. 2) Fix compute into mrf assert with
Gen5+. 3) Switch threads in system thread when writing certainarchitecture
registers. 4) Add new SetDepthBufferCoordinateOffset client interface.
|
|
BugID: 2102022,
2255316
|
Implement AutoGenMipMap for Intel® 945G Express Chipset
and Intel® G965 Express Chipset Windows Vista*.
|
Direct3D*
|
Windows* XP,
Windows Vista*
|
Intel® G965 Express Chipset,
Intel® 945G Express Chipset
|
|
Resolution Description:
Root Cause: Implement
AutoGenMipMap support for Intel® 945G Express Chipset and Intel® G965
Express Chipset Windows Vista*. Fix StretchRect failures seen in BW-G
Windows Vista* from first ETM run and DTM GetRenderTargetData failures on
BW-G Windows Vista* from second ETM.
|
|
BugID: 2292574
|
Hotplug detection does not work.
|
AIM
|
Windows* XP,
Windows Vista*
|
Intel® G965 Express Chipset
|
|
Resolution Description:
Root
Cause: When hot plug is enabled in CH7315, it generates an
interrupt. But driver does not receive this interrupt as interrupt is not
enabled in the GMCH by this time. As a result interrupt state is not
cleared in the encoder and consequently it blocks all future hot plug
interrupts. Code Changes: Since the issue is seen only with CH7315, fixed
the issue by putting a workaround in UAIMEH. Added a new function
UAIM_HotPlugInterruptWA() in UAIMEHDFP.c, which gets called after UAIM
initialization. In this function, hotplug is enabled for the output
corresponding to the pAIMObj. If there is an interrupt event at that
output, interrupt state is cleared. However, hotplug enable status is
restored before leaving this function.
|
|
BugID: 2290681
|
W - DCT5.3_QFE - Intel® G965 Express Chipset - PMTE
S3&S4 "Display settings cannot be restored" Error and
Corruption.
|
SoftBIOS
|
Windows* XP
|
Intel® G965 Express Chipset,
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: Fix memory
leak in CSurfaceManager::DestroySurface2D().
|
|
BugID: 2290646
|
Verify_PanelPowerCycleDelay_and_ReferenceRegister - Panel
values inconsistent returning from Standby (S3).
|
SoftBIOS
|
Windows* XP
|
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: Issue: While
loading LVDS registers, SB uses current values of the registers with mask.
But while doing OR operation between calculated and current values, whole
of the current value is used instead of using approriate/masked bits only.
For PannelPowerCycleDelay and Reference Register (0x61210), current values
are different while rebooting and resuming from standby, so there are
different values at the end in these scenarios. Fix: Now ensuring that
before loading LVDS registers, only appropriate bit-values are taken from
current value of the register. Also, added code for having masks depending
upon platform type. Also, added changes to remove couple of warnings in SB.
|
|
BugID: 2290642
|
Playback of WMV Clip shows corruption.
|
DVD
|
Windows* XP,
Windows Media* Center,
Windows* XP-64
|
Intel® G965 Express Chipset,
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: In VC1 advance
frofile, use the exact cropped picture size as boundary instead of MB
aligned size passed to driver as uncompressed size.
|
|
BugID: 2255639
|
W - DTM RTM - Blt - (32-bit) -
Failing Log.
|
DirectDraw*
|
Windows* XP
|
Intel® G965 Express Chipset,
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: Fix some
unfinished code. For DirectDraw* 16/32-bit depth fill blits, adjust the
destination format so it will work with GHAL2D colorfill (same as LH
DepthFill API).
|
|
BugID: 2255316
|
For performance optimization in Windows* XP and Windows
Vista*: avoid looping for blockdesc (ie., in IsLost()) by adding a flag
HasMultipleAllocations to D3DResource; set flag to true if all surface
views share a single gmmblockdescriptor.
|
Direct3D*
|
Windows* XP,
Windows Vista*
|
Intel® G965 Express Chipset
|
|
Resolution Description:
Root Cause: This code
implementation is for performance gain. We see a degradation in Windows*
XP::IsLost() where we loop through every surface view to check the block
descriptor. This loop can be avoided by adding a flag in D3DResource that
gets set if all the surfaces share a single block descriptor. Fixed subtle
bug after modifying IsLost() to be better optimized. Further optimized
IsLost() in Windows* XP and fixed BSOD on FarCry seen on Intel® G965
Express Chipset 32. Also ran FEAR, 3dMark03, and 3dMark05 using the new ETM
driver with no issues.
|
|
BugID: 2255316
|
Change outdated filter type enums in SetSamplerMinFilter
and SetSamplerMagFilter.
|
Direct3D*
|
Windows* XP,
Windows Vista*
|
Intel® G965 Express Chipset
|
|
Resolution Description:
Root Cause: This is a
side work when I work on the bug 2172184 (i.e. it is not the cause of the
bug).In D3d\ibdw\SamplerStateManager.cpp, in two functions,
SetSamplerMagFilter and SetSamplerMinFilter, outdated MAPFILTER_PYRAMIDALQUAD
and MAPFILTER_NEAREST are used, which should be D3DDDITEXF_PYRAMIDALQUAD
and D3DDDITEXF_POINT. We are using the following lookup table to convert
from Direct3D* filter to GHAL3D filter. Fortunately MAPFILTER_PYRAMIDALQUAD
(4) will be mapping to GHAL3D::SAMPLER_MAPFILTER_POINT, exactly same as
what we want. Also MAPFILTER_POINT (0) will be mapping to
GHAL3D::SAMPLER_MAPFILTER_POINT. So hardware was NOT programmed incorrectly
due to these outdated enums for filters.
|
|
BugID: 2223147
|
When system boots, noize appears after progress bar of
Windows Vista*.
|
SoftBIOS
|
Windows* XP,
Windows Vista*
|
Intel® 945GM Express Chipset,
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root Cause: Issue: We are
seeing some corruption during setmode in few customer systems. During Post,
VBIOS uses High Res Plane to display OEM Logo’s. This data in the frame
buffer is not cleared and hence the corruption. SB do not program Start
Address as part of setmode. There are cases that Start Address is not
available during setmode in Windows Vista*. Windows Vista* OS will call
Driver to BlankVideo before setmode and enables back the video after
setmode through SetSourceVisibilty DDI. But SB internally disables and
enables back the video as part of setmode. This causes the corruption. This
was required for Windows* XP to synchronize with render. The same is not
required in Windows Vista*.
Fix Description: I have added a new flag bVideoBlankingReqd in setmode
interface. Clients have to set/reset this flag based on their need.
Windows* XP setmode path has to set this flag and Windows Vista* setmode
path has to reset this flag. We need to set this flag in all cases within
SB where we use SetMode Interface.
|
|
BugID: 2211051
|
Choppy Playback with Region-2 DVD on Sonic Player.
|
DVD
|
Windows* XP,
Windows* XP-64,
Windows Media* Center
|
Intel® Q33/Q35/G33 Express Chipsets,
Intel® G965 Express Chipset,
Intel® 945GM Express Chipset,
Intel® GM965 Express Chipset,
Intel® 945G Express Chipset
|
|
Resolution Description:
Root Cause: During
deinterlacing, when the formats of current and reference samples donot
match, instead of switching from Adaptive DI to BOB, the DXVA driver was
incorrectly switching to progressive mode and causing shaking of frames.
This DCN also modifies the way content discontinuity is detected when
advanced DI(Modeast or Adaptive) is requested. Instead of checking for
renderTarget time-stamp to be within a band, it checks if the reference
sample is correct one (true prev sample).
|
|
BugID: 2197021
|
Flicker is displayed on HDTV after switching the desktop
resolution to 1766x1000 with HDTV_1080i59 video standard.
|
TVout
|
Windows* XP,
Windows Media* Center,
Windows Vista*,
Windows Vista*-64
|
Intel® GM965 Express Chipset
|
|
Resolution Description:
Root
Cause: Because 3 Tap Filter was not enabled, hence the
text readability issue.
Fix Description: 1) If the vertical filter is being used the pipe
interlace bit should be off and the TV interlace bit should be on. 2) If
the vertical filter is not being used the pipe interlace bit should be on
and the TV interlace bit should be off. 3) If Vertical filters are enabled
then we have to program the Field_swap mode (BIT15 of 68000) to Normal mode. 4) Load 3 Tap Filter Coefficients as
given by Todd. Currently only one set of coefficients is given and its
doesn’t have the granularity as found in 5 Tap filters where we have
atleast 11 sets for each of the sharpness value. 5) 3 Tap Filter needs to
be enabled only when the display’s resolution is greater than 1024.
|
|
Issues
Resolved in Build 4762
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID: 2194906,
2221920, 2287914
|
Adding SW-Tiling Copy Engine to support 384MB DVMT GPU
per surface tiling.
|
Direct3D*, DirectDraw*, DVD, GMM, OpenGL*
|
Windows* 2000, Windows* XP, Windows* 20003, Windows
Media* Center, Windows* XP-64, Windows* 20003-64, Tablet Pc
|
Intel® Q33/Q35/G33 Express Chipsets-B, Intel® G965
Express Chipset, Intel® G965 Express Chipset, Intel® 945GM Express Chipset,
Intel® GM965 Express Chipset, Intel® 945G Express Chipset, Napa
|
|
Resolution Description:
Root Cause: a setting
with which we can control the allocation system--So tiled GPU_ONLY or all
of GPU_ONLY can be disabled if necessary. Also removing the 224MB gfx mem
capping for Intel® Q33/Q35/G33 Express Chipsets.
|
|
Issues
Resolved in Build 4755
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
ID:
628889
|
Bearlake-B Power Management Fix.
|
ACPI/Power Management
|
Windows* XP, Windows* XP-64
|
Intel® Q33/Q35/G33 Chipsets
|
|
Resolution Description: Need to save full size of GTT
table.
Root Cause:
|
|
ID: 628771
|
Capture EDID raw data in diagnostic report.
|
TV Wizard, TV Wizard –
L10N
|
Windows* XP
|
Intel® Q33/Q35/G33 Chipsets
|
|
Resolution Description: With this RCR, when the user
saves the diagnostic information to a file, the Raw EDID data also will be
saved to the file.
Root Cause:
|
|
ID: 628767
|
Combined
scissor and VB optimizations.
|
OGL
|
Windows* XP, Windows* XP-64, Windows* 2000-64, Windows
Vista*, Windows Vista*-64
|
All Platforms
|
|
Resolution Description:
A combination of
optimizations involving scissor rectangle and vertex buffers that increase
the driver performance as measured by some benchmarks.
Root Cause:
|
|
ID: 629264
|
Toggle
Render Clock Throttle during Overlay use.
|
DD
|
Windows* XP
|
Intel® Q33/Q35/G33 Chipsets
|
|
Resolution Description:
Disable render
clock throttle before Overlay flip-on and enable it after Overlay flip-off.
Root Cause:
|
|
Issues
Resolved in Build 4752
|
|
Reference
No.
|
Description
|
Affected
Component(s)
|
Affected
OS(s)
|
Affected
Project(s)
|
|
BugID: 2287887
|
Enabling OpenGL* for Intel® Q33/Q35/G33 Express
Chipsets-B.
|
OpenGL*
|
Windows* XP, Windows* XP-64, Windows* 2000-64, Windows
Vista*, Windows Vista*-64
|
Intel® Q33/Q35/G33 Express Chipsets
|
|
Resolution Description:
Root Cause: 1) Set
Virtual Address bits for Memory Interface commands. 2) Do GMM allocation
for Tag Page. 3) Check for Intel® Q33/Q35/G33 Express Chipsets Device ID.
4) Remove GMM allocation for Tag page and use Miniport allocation. 5) Read
additional GMM mapped GTT offset for tag page if VTD is enabled and use
that for Store DWORD. 6) SetIndirectStateMemorySpace when state processor
is created. (new GHAL3D interface)
|
|
BugID: 2254912
|
OpenGL Driver Stability Drop 1.
|
OpenGL*
|
Windows* XP, Windows* XP-64, Windows Vista*, Windows Vista*-64
|
Intel® Q33/Q35/G33 Express Chipsets
|
|
Resolution Description:
Root Cause: OpenGL is
merging a fully tested timestamp of the OpenGL* private branch. The
following changes are included: DCN 628566
Bear Lake B A0 enabling. DCN 628617 Quake IV crash fix for low
memory setups .
|
|
BugID: 2222127
|
BSpec Violation - Multiple events occur during a
MI_WAIT_FOR_EVENT instruction.
|
DirectDraw*
|
Windows* XP, Windows* XP-64, Windows* 2000, Windows*
2000, Windows* 2000-64, Windows Media* Center.
|
All Platforms
|
|
Resolution Description:
Root Cause: This fixes
DCN #516827 which ORed in a GFX_WAIT_FLIPPENDING_B or GFX_WAIT_FLIPPENDING
to a "GFX_MI_WAIT_FOR_EVENT | GFX_WAIT_FLIPPENDING_OV". A wait
for event can only have one event/condition specified. This was causing a
hang on Intel® GM965 Express Chipset and Intel® Q33/Q35/G33 Express
Chipsets-B. Will fix by separating into two separate wait for events.
|
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